Dynamic performance adjustment of computation means

ABSTRACT

A dynamic performance circuit adjustment system and method that flexibly adjusts the performance of a logic circuit. The dynamic performance circuit adjustment system and method facilitates flexible power conservation. In one exemplary implementation, a dynamic performance adjustment control circuit controls performance adjustments to a logic circuit (e.g., a processor) and adjusts support functions for the logic circuit. The logic circuit performs operational functions (e.g., processing) or tasks that have different performance requirements. For example, some tasks performed by the logic circuit are required to be performed in a relatively short duration of time and other tasks performed by logic circuit have relatively longer time limitations. The dynamic performance adjustment control circuit adjusts the clock frequency and voltage at which the logic circuit operates to a relatively greater frequency and voltage for tasks required to be performed in a shorter duration of time and adjusts the frequency and voltage at which the logic circuit operates to a relatively lower frequency and voltage for tasks with longer timing tolerances. The dynamic performance adjustment system and method includes provisions to manage a transition in performance and support functions in a manner that reduces the risk of spurious signals or “glitches.”

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 6,721,892. The reissue applications are applicationSer. No. 11/403,243 filed on Apr. 12, 2006 and is a parent reissueapplication of U.S. Pat. No. 6,721,892, and application Ser. No.12/221,187 (the present application) filed on Jul. 30, 2008 and is acontinuation reissue application of parent reissue application Ser. No.11/403,243 filed Apr. 12, 2006 now U.S. Pat. No. Re. 40,473 of U.S. Pat.No. 6,721,892.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of computer performancemaximization. More particularly, the present invention relates tomanaging processor performance in a handheld computer with a flexiblecontrol system and method that is dynamically adaptable to achieveconservation of limited energy and power resources.

2. Related Art

Electronic systems and circuits have made a significant contributiontowards the advancement of modern society and are utilized in a numberof applications to achieve advantageous results. Numerous electronictechnologies such as digital computers, calculators, audio devices,video equipment, and telephone systems facilitate increased productivityand cost reduction in analyzing and communicating data, ideas and trendsin most areas of business, science, education and entertainment.Typically, electronic systems designed to produce these results consumepower and energy resources for these devices, such as battery powersources in portable handheld devices (e.g., a palmtop computer), areoften limited and expended quickly. Traditional attempts to conserveenergy are typically limited and do not facilitate efficient energyconservation when power demands are greater than zero but less than amaximum.

Electronic systems typically perform a wide range of tasks with highlydifferentiated processing needs. Numerous processor based electronicsystems operate at differing processing requirements or ranges. Forexample, a handheld computer (such as a Palm VII Connector Organizer)performing Personal Information Management (PIM) tasks may require aprocessor to operate at a level of one Million Instructions Per Second(MIPS), while running User Interface tasks and a radio communicationprotocol stack simultaneously may require a processor to operate at fiveto ten MIPS. Another example of differing processing levels is a V.90modem that requires approximately twice as may comparable processingcycles per unit of time (e.g., per second) as a modem which implements aslower V.34 protocol.

Typically, an electronic systems maximum capacity is designed inaccordance with the greatest task envisioned by the designers andsupport (e.g., clock speed, operating voltage, etc.) is continuouslyprovided at maximized levels. This often results in significantinefficiencies. For example, a power supply and clock typically continueto provide a maximum voltage power signal and a maximum frequency clocksignal to a processor even when the processor is capable of performing atask at a lower frequency and voltage level. Typically, the minimumfrequency and power required to adequately perform many tasks is lessthan the maximum designed clock frequencies and voltage power levels butthe electronic system continues to supply the maximum voltage powersignal and maximum frequency clock signal. For example, when a V.90capable modem is required to operate at less than its maximum speed(e.g., due to line conditions or compatibility with another modem) themaximum operational capacity to run V.90 is not utilized by the systembut support (e.g., power supply levels) is nevertheless supplied at themaximum capacity level. Continuing to provide maximum power to a deviceoperating at less than maximum capacity wastes limited energy resources.

Traditional attempts at electronic system power conservation aretypically limited to times when no processing is required and often relyon bi-static techniques that are restricted to either turning on and offa clock or power supply. For example, some traditional processingsystems attempt to conserve power by starting and stopping a processor'sclock when the processor is not required to be actively processing.Thus, it is typical for such devices to switch between a standby modewherein the processor does no processing and a fully supported mode atmaximum rates, even when a lesser degree of processing capability isadequate. Electronic systems often operate with a wide range of changingpower requirements and traditional power conservation techniques do notmaximize energy saving opportunities for varying ranges of activeprocessing. For example, in traditional electronic processing systemsthe power supply continuously supports operation at the maximum rateduring active processing and does not allow the device to variablythrottle power consumption when the processing demands are less thanmaximum but greater than zero.

Some traditional power conservation techniques attempt to increase thegranularity of performance control in electronic systems in whichfunctionality is partitioned between multiple devices, subsystems orco-processors. For example, a subsystem that is not actively processingmay be halted while another continues to function. This approach isstill limited and fundamentally bi-static in nature with regards to anyparticular subsystem or co-process, the power supply continuouslysupports operation of the particular subsystem or coprocessor at themaximum rate and does not allow the device to variably throttle powerconsumption when the processing demands on the particular subsystem orco-processor are less than maximum but greater than zero. In addition,these traditional attempts compound inefficiencies by requiring extrahardware to implement each of the multiple subsystems.

As the components required to build an electronic system have reduced insize, new categories of systems have emerged. For example, one newcategory of computer systems is the hand held or “palmtop” computersystem. A palmtop computer system is a computer that is small enough tobe held in the hand of a user and can be “palm-sized.” Most palmtopcomputer systems are used to implement various Personal InformationManagement (PIM) applications such as an address book, a daily organizerand electronic notepads, to name a few. One of the primary advantages ofa palmtop computer is mobility and the power source often comprises arelatively small internal battery with a limited life and ability tosupply energy. Inefficient power consumption often has significantadverse affects on the ease of use and the battery life of handheldcomputers.

Another issue is ease of use or the degree of user intervention requiredto manage power conservation or adjust processing performance. Requiringa user to manually adjust (e.g., turn on or off) a power consumingcircuit, for example through the graphical user interface or the buttonsof the handheld computer, is typically less preferable to automaticallyadjusting processing performance and controlling energy expenditure.Further, requiring a user to manually control a circuit (e.g., turningoff a modem) may pose problems if the user forgets or does not readjustthe controls (e.g., turn the modem on) at the appropriate time (e.g.,when a communication is sent to the user).

What is required is a system and method that dynamically adjustsperformance of a processor. The system and method should be flexiblyadaptable to various performance capabilities between a maximumperformance level and a minimum performance level. The system and methodshould provide relative power conservation while permitting processingto be performed.

SUMMARY OF THE INVENTION

The present invention system and method dynamically adjusts theperformance of a functional circuit (e.g., processor) and is flexiblyadaptable to various performance capabilities between a maximumperformance level and a minimum performance level. The dynamicperformance adjustment system and method of the present inventionprovides relative power conservation while permitting processing to beperformed. In one embodiment the present invention, a dynamicperformance adjustment system and method are implemented in a handheldcomputer.

The present invention is a dynamic performance adjustment system andmethod that flexibly adjusts the clock frequency and the voltage of afunctional circuit to adjust its performance. In one embodiment of thepresent invention, a dynamic performance adjustment system and methodfacilitates flexible power conservation. In one exemplary implementationof the present invention, a dynamic performance adjustment controlcircuit controls performance adjustments to a logic circuit (e.g., aprocessor) and adjusts support functions (e.g., power supply) for thelogic circuit. The logic circuit performs operational functions (e.g.,processing) or tasks that have different performance requirements. Forexample, some tasks performed by the logic circuit are required to beperformed in a relatively short duration and other tasks performed bylogic circuit have relatively longer time limitations. In one embodimentof the present invention, the dynamic performance adjustment controlcircuit adjusts the frequency and voltage at which the logic circuitoperates to a relatively greater frequency and voltage for tasksrequired to be performed in a shorter duration of time, and adjusts thefrequency and voltage at which the logic circuit operates to arelatively lower frequency and voltage for tasks with longer timingtolerances. In one embodiment of the present invention, a dynamicperformance adjustment system and method includes provisions to manage atransition in performance and support functions in a manner that reducesthe risk of spurious signals or “glitches.”

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one embodiment of a dynamic performancecircuit adjustment system of the present invention.

FIG. 2A is a perspective illustration of the top face of one embodimentof a hand held or palmtop computer system implementation of the presentinvention.

FIG. 2B illustrates the bottom side of one embodiment of a hand held orpalmtop computer system implementation of the present invention.

FIG. 3 is an exploded view of a hand held computer system in accordancewith one implementation of the present invention.

FIG. 4 is a block diagram of a computer system included in oneembodiment of the present invention.

FIG. 5 is a block diagram of one embodiment of a dynamic performancecircuit adjustment system of the present invention implemented in a palmcomputer system.

FIG. 6 is an illustration of one embodiment of a performancedetermination table utilized in one embodiment of the present invention.

FIG. 7 is an illustration of one embodiment of a dynamic performancecircuit adjustment system of the present invention in which a processorin a controlled logic circuit also provides performance controlprocessing functions.

FIG. 8 is a block diagram of one embodiment of a dynamic performancecircuit adjustment method of the present invention.

FIG. 9 is a flow chart of one exemplary present invention dynamicadjustment method for dynamically adjusting the performance of afunctional circuit.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of theinvention, a system and method to dynamically adjust the performance ofa processor, examples of which are illustrated in the accompanyingdrawings. While the invention will be described in conjunction with thepreferred embodiments, it will be understood that they are not intendedto limit the invention to these embodiments. On the contrary, theinvention is intended to cover alternatives, modifications andequivalents, which may be included within the spirit and scope of theinvention as defined by the appended claims. Furthermore, in thefollowing detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone ordinarily skilled in the art that the present invention may bepracticed without these specific details. In other instances, well knownmethods, procedures, components, and circuits have not been described indetail as not to unnecessarily obscure aspects of the current invention.

NOTATION AND NOMENCLATURE

Some portions of the detailed descriptions which follow are presented interms of procedures, steps, logic blocks, processing, and other symbolicrepresentations of operations on data bits that can be performed oncomputer memory. These descriptions and representations are the meansused by those skilled in the data processing arts to most effectivelyconvey the substance of their work to others skilled in the art. Aprocedure, computer executed step, logic block, process, etc., is here,and generally, conceived to be a self-consistent sequence of steps orinstructions leading to a desired result. The steps are those requiringphysical manipulations of physical quantities. Usually, though notnecessarily, these quantities take the form of electrical or magneticsignals capable of being stored, transferred, combined, compared, andotherwise manipulated in a computer system. It has proven convenient attimes, principally for reasons of common usage, to refer to thesesignals as bits, values, elements, symbols, characters, terms, numbers,or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. Unlessspecifically stated otherwise as apparent from the followingdiscussions, it is appreciated that throughout the present invention,discussions utilizing terms such as “processing” or “computing” or“translating” or “calculating” or “determining” or “scrolling” or“displaying” or “recognizing” or the like, refer to the action andprocesses of a computer system, or similar electronic computing device,that manipulates and transforms data represented as physical(electronic) quantities within the computer system's registers andmemories into other data similarly represented as physical quantitieswithin the computer system memories or registers or other suchinformation storage, transmission or display devices.

The present invention is a functional circuit (e.g., a processor, analogcircuit, etc.) performance adjustment system and method. The presentinvention facilitates adjustments to the performance of a functionalcircuit and support functions. A dynamic performance adjustment systemand method of the present invention is capable of adjusting performance(e.g., voltage and clock speed) in a manner that provides powerconservation when a task does not require a functional circuit at itsmaximum capability. In one embodiment of the present invention, adynamic performance adjustment system and method determines when themaximum capacity of a functional circuit is not required to perform atask and adjusts a power supply voltage accordingly.

FIG. 1 is a block diagram of dynamic performance circuit adjustmentsystem 100, in a accordance with one embodiment of the presentinvention. Dynamic performance circuit adjustment system 100 comprisesdynamic-performance adjustment control circuit 110 and functionalcircuit 120 (e.g., a processor, modem, amplification circuit, etc.).Dynamic performance adjustment control circuit 110 controls performanceadjustments to functional circuit 120 and adjustments of supportfunctions for functional circuit 120. Functional circuit 120 performsnormal operational functions (e.g., processing) or tasks. Differentfunctions or tasks performed by functional circuit 120 have differentperformance requirements. For example, some tasks performed byfunctional circuit 120 are required to be performed in a relativelyshort duration of time and other tasks performed by functional circuit120 have relatively longer time limitations.

In one embodiment of the present invention, dynamic performanceadjustment control circuit 110 adjusts the frequency and voltage atwhich functional circuit 120 operates to a relatively greater frequencyand voltage for tasks required to be performed in a shorter duration oftime, and adjusts the frequency and voltage at which functional circuit120 operates to a relatively lower frequency and voltage for tasks withlonger timing tolerances. For example, dynamic performance adjustmentcontrol circuit 110 adjusts the frequency and voltage at whichfunctional circuit 120 operates to a relatively greater frequency andvoltage for tasks a higher degree of processing power, and adjusts thefrequency and voltage at which functional circuit 120 operates to arelatively lower frequency and voltage for tasks requiring a lesserdegree of processing power. Thus, dynamic performance adjustment controlcircuit 110 facilitates reductions in power consumption by reducing thevoltage supplied to functional circuit 120.

In one embodiment of the present invention, dynamic performanceadjustment control circuit 110 receives a performance indication signal130 indicating the performance requirements of functional circuit 120for a particular task. Dynamic performance adjustment control circuit110 then makes an adjustment to a performance input signal 140 (e.g.,clock signal) and/or a support signal 145 (e.g., power supply signal) tofunctional circuit 120 to dynamically adjust. In one exemplaryimplementation of the present invention, dynamic performance adjustmentcontrol circuit 110 controls an adjustment to the frequency of aperformance input signal 140 (e.g., clock signal) input to functionalcircuit 120 and the voltage level of a support signal 145 (e.g., powersupply input signal) to functional circuit 120. In one embodiment of thepresent invention, dynamic performance adjustment control circuit 110stops a clock signal to functional circuit 120 and sets a functionalcircuit 120 power supply input signal to zero volts when functionalcircuit 120 is not performing operations. In one embodiment of thepresent invention, dynamic performance adjustment control circuit 110comprises a processor. In one embodiment of the present invention,dynamic performance adjustment control circuit 110 comprises a statemachine.

In one embodiment of the present invention, dynamic performanceadjustment control circuit 110 manages adjustment timing to facilitatethe reduction of errors or glitches. In one embodiment of the presentinvention, functional circuit 120 ceases active operations while dynamicperformance adjustment control circuit 110 makes changes to performance(e.g., clock rates) and/or support functions (e.g., power supplyvoltages). Ceasing functional circuit 120 operations during thestabilization period reduces the risk of adverse impact from glitches orfluctuations resulting from clock generation and/or clock controlcircuits that generate spurious signals while changing frequencies.Similarly, preventing functional circuit 120 from performing operationsduring the stabilization period also reduces the risk of errorsassociated with changing voltages during functional circuit 120executions, whether implemented internally or externally to anintegrated circuit.

In one embodiment of the present invention, dynamic performanceadjustment control circuit 110 facilitates the reduction of errors orglitches on the fly without a functional circuit ceasing operations. Insome exemplary implementation the present invention comprises “glitcheaters”. For example, Schmidt triggers that clean edges of a signal ifthey are not full magnitude or utilizing capacitor elements. Anotherembodiment includes a clock divider that divides a clock signal, thedivide division gives more stability because additional pulses in thedivided down forma are narrower and it is not as critical if there is anextra pulse. In yet another embodiment of the present invention, a firstwaveform is combined with a second waveform through a logic AND andgenerates a minimum clock period to prevent smaller pulses.

In one embodiment of the present invention, dynamic performanceadjustment control circuit 110 transmits an operation control signal 150to functional circuit 120. Operation control signal 150 directsfunctional circuit 120 to cease operations for a period of timesufficient to permit dynamic performance adjustment control circuit 110to make changes to performance input signal 140 and/or support signal145 and permit the system to stabilize. Functional circuit 120 signalsdynamic performance adjustment control circuit 110 to change performanceand/or support functions and then ceases active operation. After makingthe changes and the system has sufficiently stabilized, dynamicperformance adjustment control circuit 110 transmits an operationcontrol signal 150 notifying functional circuit 120 to resumeoperations.

A dynamic performance circuit adjustment system of the present inventionis also applicable to variety of analog embodiments. In one exemplaryimplementation, a dynamic performance circuit adjustment system of thepresent invention is utilized in an analog system (e.g., a Walkmanportable radio) to adjust the operating voltage of a functional circuit(e.g., an amplifier circuit) in accordance with a performancerequirement. For example, the voltage of an amplification circuit isincreased to accommodate greater frequency or volume requirements anddeceased to conserve power when lower frequency or volume is adequate.

A dynamic performance circuit adjustment system is flexibly adaptable toa variety of implementations, for example a portable or palmtopcomputer. FIG. 2A is a perspective illustration of the top face 200a ofone embodiment of a hand held or palmtop computer system. The top face200a contains a display screen 205 surrounded by a bezel or cover. Aremovable stylus 280 and on/off button 295 are also shown. The displayscreen 205 is a touch screen able to register contact between the screenand the tip of the stylus 280. The top face 200a also contains one ormore dedicated and/or programmable buttons 275 for selecting informationand causing the computer system to implement functions. FIG. 2A alsoillustrates a handwriting recognition pad or “digitizer” containing tworegions 206a and 206b. Region 206a is for the drawing of alphacharacters therein for automatic recognition and region 206b is for thedrawing of numeric characters therein for automatic recognition. Thestylus 280 is used for stroking a character within one of the regions206a and 206b. The stroke information is then fed to an internalprocessor for automatic character recognition. Once characters arerecognized, they are typically displayed on the screen 205 forverification and/or modification.

FIG. 2B illustrates the bottom side 200b of one embodiment of a handheld or palmtop computer system. An optional extendible antenna 285, abattery storage compartment door 290, and a serial communicationinterface 208 are shown. Extendible antenna 285 is utilized for wirelesscommunications (e.g., cellular phone, radio, etc.). Battery storagecompartment door 290 provides access for battery replacement. Serialcommunication interface 208 provides a communication port forcommunications with peripheral devices (e.g., a palm cradle, landlinephone modem, etc.).

FIG. 3 is an exploded view of the hand held computer system 300 inaccordance with one implementation of the present invention. Hand heldcomputer system 300 includes front cover 310 having an outline of region306 and holes 375a for receiving buttons 375b. A flat panel display 305(both liquid crystal display and touch screen) fits into front cover310. Any of a number of display technologies can be used (e.g., LCD,FED, plasma, etc.) for the flat panel display 305. A battery 315provides electrical power. A contrast adjustment (potentiometer) 320 isalso shown. On/off button 395 is shown along with an infrared emitterand detector device 364. A flex circuit 330 is shown along with a PCboard 325 containing electronics and logic (e.g., memory, communicationbus, processor, etc.) for implementing computer system functionality.The digitizer pad is also included in PC board 325. A midframe 335 isshown along with stylus 380.

Hand held computer system 300 is capable of communicating with otherdevices. Position adjustable antenna 385 for transmitting and receivingcommunication signals is shown. A radio receiver/transmitter device 340is also shown between the midframe and the rear cover 345 of FIG. 3. Thereceiver/transmitter device 340 is coupled to the antenna 385 and alsocoupled to communicate with the PC board 325. In one implementation ofthe present invention, the Mobitex wireless communication system is usedto provide two way communication between system 300 and other networkedcomputers and/or the Internet via a proxy server. Communicationinterface 377 is coupled to PC board 325 and provides a communicationsport (e.g., a serial port) for communicating signals to and from aperipheral device.

FIG. 4 is a block diagram of computer system 400, some of which isimplemented on PC board 325. Computer system 400 includes address/databus 410, central processor 401, volatile memory 402 (e.g., random accessmemory RAM), non-volatile memory 403 (e.g., read only memory ROM),optional removable data storage device 404 (e.g., memory stick), displaydevice 405, optional alphanumeric input device 406, optional cursorcontrol or directing device 407, and signal communication port 408,modem 409 and main dynamic control adjustment circuit 110 411.Address/data bus 410 is coupled to central processor 401, volatilememory 402 (e.g., random access memory RAM), non-volatile memory 403(e.g., read only memory ROM), optional removable data storage device 404(e.g., memory stick), display device 405, optional alphanumeric inputdevice 406, optional cursor control or directing device 407, and signalcommunication port 408, modem 409 and main dynamic control adjustmentcircuit 110 411. In one embodiment of the present invention, centralprocessor 401 includes main dynamic control adjustment circuit 110 411.

The components of computer system 400 cooperatively function to providea variety of functions, including PIM, communications, etc. Address/databus 410 communicates information, central processor 401 processesinformation and instructions, volatile memory 402 (e.g., random accessmemory RAM) stores information and instructions for the centralprocessor 401 and non-volatile memory 403 (e.g., read only memory ROM)stores static information and instructions. Optional removable datastorage device 404 (e.g., memory stick) also stores information andinstructions. Display device 405 displays information to the computeruser and an optional alphanumeric input device 406 is an input device,which in one implementation is a handwriting recognition pad(“digitizer”) having regions 306a and 306b (see FIG. 3A). Optionaldirecting device 407 also communicates user input information andcommand selections to the central processor 401 via a touch screencapable of registering a position on the screen 405 where the stylusmakes contact. Signal Communication port 408 is a communicationinterface (e.g., serial communications port 308) for communicatingsignals to and from a coupled peripheral device (not shown). Modem 409facilitates communications with other devices. Main dynamic controladjustment circuit 110 411 controls adjustments to the performance ofother components (e.g., processor 410, modem 409, etc.) and comprises avariety of configurations in different implementations. In oneembodiment of the present invention, main dynamic control adjustmentcircuit 110 411 controls adjustments to the support functions (e.g.,power supplies) to other components.

FIG. 5 is block diagram of dynamic performance circuit adjustment system500 in accordance with one embodiment of the present invention. In oneembodiment of the present invention, dynamic performance circuitadjustment system 500 is implemented in palm computer system 300.Dynamic performance circuit adjustment system 500 comprises main dynamicadjustment control circuit 550, clock circuit 520, voltage supplycircuit 530, and logic circuit 570. Clock circuit 520 comprises a highfrequency output 521 and a low frequency output 522. Voltage supplycircuit 530 comprises high voltage output 531 and low voltage output532. Main dynamic adjustment control circuit 550 is coupled to clockcircuit 520, voltage supply circuit 530, and logic circuit 570. Logiccircuit 570 is coupled to clock circuit 520, voltage supply circuit 530.

The components of dynamic performance circuit adjustment system 500cooperatively operate to provide flexible dynamic performance adjustmentof logic circuit 570. Logic circuit 570 performs operational functions(e.g., processing) or tasks. Clock circuit 520 supplies a clock signal581 to logic circuit 570. Clock signal 581 is a first relatively highfrequency or second relatively low frequency depending upon whether highfrequency output 521 or low frequency output 522 is enabled. Voltagesupply circuit 530 supplies a power signal 582 to logic circuit 570.Power signal 582 is a first relatively high voltage or a secondrelatively low voltage depending upon whether high voltage output 521 orlow voltage output 532 are enabled. Main dynamic adjustment controlcircuit 550 controls adjustments to the performance of logic circuit570. For example, main dynamic adjustment control circuit 550 enableseither high frequency output 521 via high frequency enable signal 591 orlow frequency output 522 via low frequency enable signal 592. Similarlymain dynamic adjustment control circuit 550 enables either high voltageoutput 531 via high voltage enable signal 593 or low voltage output 532via low voltage enable signal 594. At lower voltage settings, dynamicperformance circuit adjustment system 500 facilitates powerconservation.

A dynamic performance adjustment power control system of the presentinvention provides a significant degree of flexibility in adjustingperformance (e.g., computation performance or speed of a processor). Adynamic performance adjustment power control system of the presentinvention is easily expanded to provide greater granularity of control.For example, in one embodiment of the present invention a clock circuithas numerous different frequency outputs that are controlled by a maindynamic performance adjustment control circuit. Similarly, in oneembodiment of the present invention a power supply has numerousdifferent voltage outputs (e.g., 5 volts, 3.3 volts, 2 volts, 0 volts,etc.) that are controlled by a main dynamic performance adjustmentcontrol circuit. Dynamic performance circuit adjustment system 500“throttles” between the different voltage outputs depending uponperformance requirements to conserve power when less than maximumperformance is required.

In one embodiment of the present invention, a main dynamic performanceadjustment control circuit disables a clock signal and/or a power signalto logic circuit 570. Main dynamic adjustment control circuit 550 (FIG.5) disables both high frequency output 521 and low frequency output 522turning off the clock signal to logic circuit 570. Similarly, maindynamic adjustment control circuit 550 also disables both high voltageoutput 531 and low voltage output 532 reducing power supplied to logiccircuit 570.

A dynamic performance adjustment control circuit (e.g., main dynamicadjustment control circuit 550 shown in FIG. 5) comprises a variety ofconfigurations or embodiments. For example, a dynamic performanceadjustment control circuit comprises a processor in one embodiment ofthe present invention. In another exemplary implementation, the dynamicperformance adjustment control circuit comprises a state machine. Thedynamic performance adjustment control circuit dynamically adjusts theperformance of a logic circuit (e.g., a processor) based upon therequirements of a particular task. In one exemplary implementation ofthe present invention, the dynamic performance adjustment controlcircuit determines an optimized clock rate and power supply voltagebased upon the particular task to be performed by the logic circuit. Inone embodiment, a processor included in a dynamic performance adjustmentcontrol circuit utilizes a hash table to determine appropriateperformance controls and support functions.

FIG. 6 is an illustration of performance determination table 600 thatcan be used in one embodiment of the present invention. Performancedetermination table 600 tracks seven different tasks performed by alogic circuit and provides a correlation to their associated performanceand support requirements. A first task requires maximum frequency andvoltage and a processor in dynamic performance adjustment controlcircuit signals a frequency supply and voltage supply to provide amaximum frequency and voltage to the logic circuit. A second and sixthtask require a relatively high frequency and voltage and a processor indynamic performance adjustment control circuit signals a frequencysupply and voltage supply to provide a relatively high frequency andvoltage to the logic circuit. A third and seventh task require arelatively low frequency and voltage and a processor in dynamicperformance adjustment control circuit signals a frequency supply andvoltage supply to provide a relatively low frequency and voltage to thelogic circuit. A forth task does not require maximum capacity of thelogic circuit, however the performance is optimized by providing amaximum frequency and voltage for a period of time and turning off afrequency and voltage supply after the task is performed. The dynamicperformance adjustment control circuit turns the frequency supply andpower supply on when another task is required. A fifth task does notrequire the logic circuit to perform any functions and the dynamicperformance adjustment control circuit turns off a frequency supply andvoltage supply until the logic circuit is required to perform anothertask.

The present invention is very flexible in managing power consumption andfacilitates the weighing of a number of factors in controlling theperformance of a logic circuit such as a processor. One exemplaryembodiment of the present includes a hash table in which multiplefactors weighed in determining a task number. For example, a particularfunctional task may have a higher priority at times and a lower priorityat others. The functional task is assigned different task numbers in thehash table according to the priority requirements, a higher prioritytask is assigned a task number associated with performing the functionaltask quickly (e.g., task number 4) and a lower priority task is assignedanother task number associated with performing the functional taskslower (e.g. task number 3).

In one embodiment of the present invention, the dynamic performanceadjustment control circuit adjusts the performance of a processor in amodem in accordance with an appropriate communication rate. In thisexemplary implementation, a modem initiates a communication session byengaging in a handshaking protocol in which a communication rate isnegotiated based upon a number of parameters (e.g., the maximum baudrates of the modems on each end, line conditions, etc.). The negotiatedcommunication rate is supplied to the dynamic performance adjustmentcontrol circuit. Based upon the negotiated communication rate thedynamic performance adjustment control circuit determines the optimalmodem processor rate. The optimal processor rate is the lowest rate atwhich the modem processor adequately services a negotiated communicationrate.

In one exemplary implementation of the present invention, the dynamicperformance adjustment control circuit adjusts the performance of aprocessor in a modem that normally operates at a maximum 56K bits persecond (bps). The modem processor requires a clock signal at arelatively high frequency to service the 56 Kbps rate. The dynamicperformance adjustment control circuit enables a relatively highfrequency output of a clock circuit and a relatively high voltage outputof a power supply. However, if the negotiated communication rate is 28.8Kpbs, the modem processor is capable servicing the 28.8 Kbps rate basedupon a clock signal at a relatively low frequency and a dynamicperformance adjustment control circuit enables a relatively lowfrequency output of a clock circuit and a relatively low voltage outputof a power supply. In one embodiment of the present invention, a dynamicperformance adjustment control circuit disables all clock outputs andpower supply outputs when the modem is not actively engaged intransmitting or receiving data.

One embodiment of the present invention utilizes a processor included inthe logic circuit to perform a dynamic performance adjustment controlcircuit. FIG. 7 is an illustration of dynamic performance circuitadjustment system 700. Dynamic performance circuit adjustment system 700comprises logic circuit 705, clock control switch 740 and power supplyswitch 750. Logic circuit 705 is coupled to clock control switch 740 andpower supply switch 750. Logic circuit 705 comprises processor 710 whichperforms operational functions or tasks as well as providing and dynamicadjustment control processing. The dynamic adjustment control processingissues a clock control signal 722 to clock control switch 740 and avoltage control signal 732 to power supply switch 750. Clock controlsignal 722 controls whether clock control switch selects to transmit X1Mhx or X2 Mhz signal as clock signal 721. Voltage control signal 732controls whether power supply switch selects to transmit V1 voltagesignal or V2 voltage signal as power supply signal Vcc 731.

In one embodiment, 700, logic circuit 705 comprises a power controlstate machine (not shown) adjacent to processor 710. The power controlstate machine (not shown) is included in the same integrated circuit(IC). The power control state machine resists errors caused by changingsupport functions (e.g., voltage of a power supply signal) and/orperformance (e.g., a clock rate). Processor 710 signals the powercontrol state machine to change operating condition(s) and then theprocessor 710 ceases active operation. The power control state machinewaits a predetermined time period (e.g., number of clock cycles) andthen initiate and control the changes. In one embodiment of the presentinvention, after a second predetermined time sufficient to permit theclock generator and/or voltage generator to stabilize, the power controlstate machine signals processor 710 to resume active operation.

FIG. 8 is a block diagram of dynamic performance circuit adjustmentmethod 800, in accordance with one embodiment of the present invention.Dynamic performance circuit adjustment method 800 provides flexiblecontrol of a functional circuit by facilitating adjustments to theperformance of a functional circuit (e.g., a digital processor, analogamplifier, etc.) and support functions (e.g., power signals). Dynamicperformance circuit adjustment method 800 is capable of adjustingperformance in a manner that provides power conservation when afunctional circuit is required to actively execute tasks at a rate lowerthan its maximum capability.

In step 810, an appropriate performance level (e.g., processingfrequency, communication rate, etc.) is determined. In one embodiment ofthe present invention, the minimum level (e.g., frequency, voltage,etc.) at which a functional circuit adequately performs a task, (e.g.,processing, modem communication, etc.) is considered an appropriateperformance level. In exemplary implementation, an appropriateperformance level is to operate at maximum capacity for a period of timeand then throttle back for a period of time.

In step 820, an appropriate support level (e.g., voltage of a powersupply signal) is determined. In one embodiment of the presentinvention, an appropriate voltage level of a power supply signals isdetermined based upon the frequency of a clock signal. For example, thehigher the frequency of a clock signal the higher the appropriatevoltage level of a power supply signal.

In step 830, a performance indication signal (e.g., performanceindication signal 130) is received. The performance indication signalindicates the performance requirements of a functional circuit (e.g.,functional circuit 120) for a particular task. In one embodiment of thepresent invention, a performance indication signal indicates anegotiated communication rate (e.g., a modem communication rate) or thespeed at which a processor operates to adequately accommodate anegotiated communication rate.

In Step 840, a functional circuit ceases operations during astabilization period. In one embodiment of dynamic performance circuitadjustment method 800, a functional circuit is directed to ceaseoperations for a period of time sufficient to permit a dynamicperformance adjustment control circuit to make changes to a performanceinput signal (e.g., a clock signal) and a support signal (e.g., a powersignal) and permit the system to stabilize. Dynamic performance circuitadjustment method 800 makes changes to clock rates and or operatingvoltages while a functional circuit is not actively operating. Afunction circuit ceases operations for a predetermined period of time.

In step 850, a performance signal is adjusted. For example, the clocksignal frequency can be adjusted by performance circuit adjustmentmethod 800. In one embodiment of the present invention, the clock signalfrequency is adjusted by enabling a first relatively high frequencyclock output (e.g., turning on a relatively high frequency clock ormaking adjustments in clock multiplier or divider). The clock signalfrequency can be adjusted by enabling a second relatively low frequencyclock output (e.g., turning on a relatively low frequency clock ormaking adjustments in clock multiplier or divider). In one embodiment ofthe present invention, a performance signal is adjusted by switchingbetween a low frequency source and a high frequency source.

In step 860, a support signal is adjusted. In one exemplaryimplementation of the present invention, a power signal voltage isadjusted by performance circuit adjustment method 800. The power signalvoltage is adjusted by enabling a first relatively high voltage signaloutput (e.g., turning on a relatively high voltage source or making). Inone embodiment of the present invention, the power signal voltage isadjusted by enabling a second relatively low voltage signal output(e.g., turning on a relatively low voltage source). A power signal isadjusted by switching between a low voltage source and a high voltagesource. In one embodiment of the present invention, enabling a secondrelatively low voltage signal output or switching to a low voltagesource conserves power.

In step 870 the process returns to step 810.

FIG. 9 is a flow chart of dynamic adjustment method 900, a presentinvention method of dynamically adjusting the performance of afunctional circuit. In one embodiment of the present invention,utilizing dynamic adjustment method 900 to adjust performancefacilitates power conservation. For example, dynamic adjustment method900 adjusts the frequency at which a functional circuit performs andchanges the voltage level of a power supply signal accordingly tosupport the frequency change. Thus, dynamic adjustment methodfacilitates power conservation during tasks requiring a lower voltagepower signal.

In Step 910, a performance indication signal is accessed. Theperformance indication signal provides an indication of an adequate ordesired performance level of a functional circuit (e.g., functionalcircuit 120)

In Step 920 a voltage level and clock frequency are dynamicallydetermined based upon the performance signal accessed in Step 910. Forexample, a clock frequency and power supply voltage level are set to amaximum value if a performance indication signal indicates thefunctional circuit

In Step 930 a functional circuit performance level is dynamicallyadjusted by supplying the voltage level and clock frequency dynamicallydetermined in Step 920. In one embodiment of the present invention,different voltage level power signals and clock frequency signals areselectively enabled. In one implementation, dynamic adjustment method900 switches between different voltage level power signals and clockfrequency signals. A functional circuit to cease operations for a periodof time sufficient to permit a functional circuit to stabilize before aperformance level adjustment.

In Step 940, a functional circuit performs a task at the performancelevel indicated by the performance indication signal accessed in Step910. In one exemplary implementation a processor performs computationsat a frequency slower than its maximum permitting it to operate at avoltage level less than its maximum and thus conserves power.

In Step 950 the process returns to Step 910.

Thus, the present invention system and method dynamically adjusts theperformance of a functional circuit (e.g., processor) and is flexiblyadaptable to various performance capabilities between a maximumperformance level and a minimum performance level. The dynamicperformance adjustment system and method of the present inventionprovides relative power conservation while permitting processing to beperformed. The present invention is adaptable to a variety ofimplementations, for example a handheld palm computer. In one exemplaryimplementation, the present invention is utilized to control performanceand functional support adjustments to a functional circuit comprisinganalog components. In one embodiment of the present invention, a dynamicperformance adjustment control circuit controls adjustments to operatingvoltages of an amplification circuit of a Walkman portable radio asfrequency and/or loudness requirements change.

The foregoing descriptions of specific embodiments of the presentinvention have been presented for purposes of illustration anddescription. They are not intended to be exhaustive or to limit theinvention to the precise forms disclosed, and obviously manymodifications and variations are possible in light of the aboveteaching. The embodiments were chosen and described in order to bestexplain the principles of the invention and its practical application,to thereby enable others skilled in the art to best utilize theinvention and various embodiments with various modifications as aresuited to the particular use contemplated. It is intended that the scopeof the invention be defined by the Claims appended hereto and theirequivalents.

What is claimed is:
 1. A dynamic performance circuit adjustment systemcomprising: a functional circuit for performing operational tasks thathave differing minimum performance and support function requirements;and a dynamic performance adjustment control circuit for controllingperformance adjustments to said functional circuit and adjustments tosupport functions for said functional circuit, said dynamic performanceadjustment control circuit coupled to said functional circuit, whereinsaid dynamic performance adjustment control circuit: a) adjusts thefrequency and voltage at which said functional circuit operates to arelatively greater frequency and voltage for tasks required to beperformed in a shorter duration of time, b) adjusts the frequency andvoltage at which said functional circuit operates to a relatively lowerfrequency and voltage for tasks with longer timing tolerance, and c)transmits an operation control signal to said functional circuitdirecting said functional circuit to cease operations for a period oftime sufficient to permit said dynamic performance adjustment controlcircuit to make changes to said performance input signal and saidsupport signal and permit the system to stabilize.
 2. The dynamicperformance circuit adjustment system of claim 1 wherein said dynamicperformance adjustment control circuit receives a performance indicationsignal indicating said minimal performance requirements of saidfunctional circuit for a particular one of said tasks.
 3. The dynamicperformance circuit adjustment system of claim 2 wherein said dynamicperformance adjustment control circuit makes an adjustment to aperformance signal and a support signal for said functional circuit inaccordance with said performance indication signal indicating.
 4. Thedynamic performance circuit adjustment system of claim 1 wherein saiddynamic performance adjustment control circuit stops a clock signal tosaid functional circuit and sets a power supply signal to saidfunctional circuit at zero volts when said functional circuit is notactively performing operation.
 5. The dynamic performance circuitadjustment system of claim 1 wherein said functional circuit signalssaid dynamic performance adjustment control circuit to adjustperformance and support functions for said functional circuit and saidfunctional circuit ceases active operation for a period of timesufficient to permit said dynamic performance adjustment control circuitto make changes to said performance input signal and said support signaland permit the system to stabilize.
 6. A dynamic performance circuitadjustment system implemented in a palm computer system comprising; alogic circuit for performing operational functions or tasks; a clockcircuit for supplying a clock signal to said logic circuit, said clockcircuit coupled to said logic circuit; a voltage supply circuit forsupplying a power signal to said logic circuit, said voltage supplycircuit coupled to said logic circuit; and a main dynamic adjustmentcontrol circuit for controlling the performance of said logic circuit byvarying a frequency of said clock signal and by varying the voltage ofsaid power signal, wherein said main dynamic adjustment control circuitsignals said logic circuit to cease active operations for a period oftime sufficient to permit said dynamic performance adjustment controlcircuit to make changes to said frequency and said voltage and andpermit the system to stabilize, said main dynamic adjustment controlcircuit coupled to said logic circuit.
 7. The dynamic performancecircuit adjustment system of claim 6 wherein said clock circuit furthercomprises: a high frequency output for supplying a first relatively highfrequency signal; and a low frequency output for supplying a secondrelatively low frequency signal.
 8. The dynamic performance circuitadjustment system of claim 6 wherein said voltage supply circuit furthercomprises: a high voltage output for supplying a first relatively highvoltage signal; and a low voltage output for supplying a firstrelatively low voltage signal.
 9. The dynamic performance circuitadjustment system of claim 6 wherein said main dynamic adjustmentcontrol circuit selectively enables a high frequency output via a highfrequency enable signal and a low frequency output via a low frequencyenable signal.
 10. The dynamic performance circuit adjustment system ofclaim 6 wherein said main dynamic adjustment control circuit selectivelyenables a high voltage output via a high voltage enable signal and a lowvoltage output via a low voltage enable signal.
 11. The dynamicperformance circuit adjustment system of claim 6 wherein saidperformance adjustment control circuit disables a clock signal and apower signal to logic circuit.
 12. A dynamic performance circuitadjustment method comprising the steps of: a) accessing a performanceindication signal; b) based upon said performance indication signal,dynamically determining a voltage level and a clock frequency; c)supplying said voltage level and said clock frequency to said functionalcircuit to dynamically adjust its performance level and directingfunctional operations to cease for a period of time sufficient to permitstabilize before adjusting said performance level; d) performing a taskusing said factional circuit; and e) repeating steps a) through d). 13.A method of claim 12 further comprising the step of ceasing functionalcircuit active operation during stabilization period.
 14. A method ofclaim 12 further comprising the steps of: c1) selecting a firstrelatively high frequency clock output; and c2) selecting a secondrelatively low frequency clock output.
 15. A dynamic performance circuitadjustment method of claim 12 wherein step c) further comprises the stepof switching between a low frequency source and a high frequency source.16. A method of claim 12 wherein step c) further comprises the steps of:enabling a first relatively high voltage signal output; and enabling asecond relatively low voltage signal output.
 17. A method of claim 12wherein step c) further comprises the step of switching between a lowvoltage source and a high voltage source.
 18. A dynamic performanceadjustment system comprising: a display operable to display informationthereon; a memory device; a functional circuit for performingoperational tasks that have differing minimum frequency and voltagerequirements; and a dynamic performance adjustment control circuit forcontrolling at least one of frequency adjustment and voltage adjustmentto said functional circuit, said dynamic performance adjustment controlcircuit coupled to said functional circuit, wherein said dynamicperformance adjustment control circuit: a) adjusts at least one offrequency and voltage at which said functional circuit operates to atleast one of a relatively greater frequency and a relatively greatervoltage for tasks required to be performed in a shorter duration oftime, b) adjusts at least one of frequency and voltage at which saidfunctional circuit operates to at least one of a relatively lowerfrequency and a relatively lower voltage for tasks with longer timingtolerance, and c) transmits an operation control signal to saidfunctional circuit directing said functional circuit to cease operationsfor a period of time sufficient to implement a change to said frequencyand said voltage supplied to said functional circuit, said period oftime permitting said dynamic performance adjustment control circuit tocontrol at least one of frequency adjustment and voltage adjustment tosaid functional circuit and permitting said dynamic performanceadjustment system to stabilize.
 19. The dynamic performance adjustmentsystem of claim 18, wherein said period of time is sufficient to permitsaid dynamic performance adjustment control circuit to control bothfrequency adjustment and voltage adjustment to said functional circuit.20. The dynamic performance adjustment system of claim 18, wherein saiddynamic performance adjustment control circuit receives a performanceindication signal indicating a minimal performance requirement of saidfunctional circuit for a particular one of said operational tasks. 21.The dynamic performance adjustment system of claim 20, wherein saiddynamic performance adjustment control circuit controls at least one offrequency adjustment and voltage adjustment to said functional circuitin accordance with said performance indication signal.
 22. The dynamicperformance adjustment system of claim 18, wherein said dynamicperformance adjustment control circuit stops a clock signal to saidfunctional circuit and sets a power supply signal to said functionalcircuit at substantially zero volts when said functional circuit is notactively performing an operation.
 23. The dynamic performance adjustmentsystem of claim 18, wherein said functional circuit signals said dynamicperformance adjustment control circuit to control at least one offrequency adjustment and voltage adjustment for said functional circuit,and wherein said functional circuit ceases operation for a period oftime sufficient to permit said dynamic performance adjustment controlcircuit to control at least one of frequency adjustment and voltageadjustment to said functional circuit and permit the dynamic performanceadjustment system to stabilize.
 24. The dynamic performance adjustmentsystem of claim 18, further comprising a bus.
 25. The dynamicperformance adjustment system of claim 24, wherein said memory device iscoupled to said bus.
 26. The dynamic performance adjustment system ofclaim 25, wherein said dynamic performance adjustment control circuit iscoupled to said bus.
 27. The dynamic performance adjustment system ofclaim 18, further comprising an input device.
 28. The dynamicperformance adjustment system of claim 18, further comprising acommunication device for communicating signals.
 29. The dynamicperformance adjustment system of claim 18, further comprising a powersource.
 30. A mobile computer system comprising: a display fordisplaying information; a memory unit; a logic circuit for performingoperational functions or tasks; a clock circuit for supplying a clocksignal to said logic circuit, said clock circuit coupled to said logiccircuit; a voltage supply circuit for supplying a power signal to saidlogic circuit, said voltage supply circuit coupled to said logiccircuit; and a dynamic adjustment control circuit for controlling theperformance of said logic circuit by varying at least one of a frequencyof said clock signal and a voltage of said power signal to said logiccircuit, wherein said dynamic adjustment control circuit signals saidlogic circuit to cease active operations for a period of time sufficientto implement a change to said frequency and said voltage supplied tosaid logic circuit, said period of time permitting said dynamicadjustment control circuit to vary at least one of said frequency ofsaid clock signal and said voltage of said power signal and permittingthe mobile computer system to stabilize, said dynamic adjustment controlcircuit being coupled to said logic circuit.
 31. The mobile computersystem of claim 30, wherein said clock circuit further comprises: a highfrequency output for supplying a high frequency signal; and a lowfrequency output for supplying a low frequency signal.
 32. The mobilecomputer system of claim 31, wherein said voltage supply circuit furthercomprises: a high voltage output for supplying a high voltage signal;and a low voltage output for supplying a low voltage signal.
 33. Themobile computer system of claim 32, wherein said dynamic adjustmentcontrol circuit selectively enables said high frequency output via ahigh frequency enable signal and said low frequency output via a lowfrequency enable signal.
 34. The mobile computer system of claim 33,wherein said dynamic adjustment control circuit selectively enables saidhigh voltage output via a high voltage enable signal and said lowvoltage output via a low voltage enable signal.
 35. The mobile computersystem of claim 30, wherein said dynamic adjustment control circuitdisables said clock signal and said power signal to said logic circuit.36. The mobile computer system of claim 30, further comprising an inputdevice for receiving user input.
 37. The mobile computer system of claim30, further comprising a communication device for communicating signals.38. The mobile computer system of claim 30, further comprising a powersource.
 39. A method comprising: a) accessing a performance indicationsignal within a computer system including a display, a memory unit, anda functional circuit; b) based upon said performance indication signal,dynamically determining at least one of a voltage level and a clockfrequency for said functional circuit; c) supplying at least one of saidvoltage level and said clock frequency to said functional circuit todynamically adjust a performance level for said functional circuit anddirecting said functional circuit to cease functional operations for aperiod of time sufficient to implement a change to said voltage leveland said clock frequency supplied to said functional circuit, saidperiod of time permitting stabilization before adjustment of saidperformance level; d) performing a task using said functional circuit;and e) repeating said a) through d).
 40. The method of claim 39, whereinsaid c) comprises: enabling one of a high frequency clock output and alow frequency clock output.
 41. The method of claim 39, wherein said c)comprises: switching between a low frequency source and a high frequencysource.
 42. The method of claim 39, wherein said c) comprises: enablingone of a high voltage signal output and a low voltage signal output. 43.The method of claim 39, wherein said c) comprises: switching between alow voltage source and a high voltage source.
 44. The method of claim39, wherein said computer system further includes a user input device.45. The method of claim 39, wherein said computer system furtherincludes a user input device.
 46. The method of claim 39, wherein saidcomputer system further includes a power source.
 47. A dynamicperformance adjustment system comprising: a display operable to displayinformation thereon; a memory device; a functional circuit forperforming operational tasks that have differing minimum frequency andvoltage requirements; and a dynamic performance adjustment controlcircuit for controlling frequency adjustment and voltage adjustment tosaid functional circuit, said dynamic performance adjustment controlcircuit coupled to said functional circuit, wherein said dynamicperformance adjustment control circuit: a) adjusts frequency and voltageat which said functional circuit operates to a relatively greaterfrequency and a relatively greater voltage for tasks required to beperformed in a shorter duration of time, b) adjusts frequency andvoltage at which said functional circuit operates to a relatively lowerfrequency and a relatively lower voltage for tasks with longer timingtolerance, and c) transmits an operation control signal to saidfunctional circuit directing said functional circuit to cease operationsfor a period of time sufficient to implement a change to said frequencyand said voltage supplied to said functional circuit, said period oftime permitting said dynamic performance adjustment control circuit tocontrol frequency adjustment and voltage adjustment to said functionalcircuit and permitting said dynamic performance adjustment system tostabilize.
 48. The dynamic performance adjustment system of claim 47,wherein said dynamic performance adjustment control circuit receives aperformance indication signal indicating a minimal performancerequirement of said functional circuit for a particular one of saidoperational tasks.
 49. The dynamic performance adjustment system ofclaim 48, wherein said dynamic performance adjustment control circuitcontrols frequency adjustment and voltage adjustment to said functionalcircuit in accordance with said performance indication signal.
 50. Thedynamic performance adjustment system of claim 47, wherein said dynamicperformance adjustment control circuit stops a clock signal to saidfunctional circuit and sets a power supply signal to said functionalcircuit at substantially zero volts when said functional circuit is notactively performing an operation.
 51. The dynamic performance adjustmentsystem of claim 47, wherein said functional circuit signals said dynamicperformance adjustment control circuit to control frequency adjustmentand voltage adjustment for said functional circuit, and wherein saidfunctional circuit ceases operation for a period of time sufficient topermit said dynamic performance adjustment control circuit to controlfrequency adjustment and voltage adjustment to said functional circuitand permit the dynamic performance adjustment system to stabilize. 52.The dynamic performance adjustment system of claim 47, furthercomprising a bus.
 53. The dynamic performance adjustment system of claim52, wherein said memory device is coupled to said bus.
 54. The dynamicperformance adjustment system of claim 53, wherein said dynamicperformance adjustment control circuit is coupled to said bus.
 55. Thedynamic performance adjustment system of claim 47, further comprising aninput device.
 56. The dynamic performance adjustment system of claim 47,further comprising a communication device for communicating signals. 57.The dynamic performance adjustment system of claim 47, furthercomprising a power source.